CS5528-ASZR【PDF 3/56 页】IC ADC 24BIT 8CH 24-SSOP

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Sheet目录1991

1页 2页 [3页]4页 5页 6页 7页

CS5521/22/23/24/28

DS317F8

SWITCHING CHARACTERISTICS (T

A = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;

Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF.))

Notes: 25. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 200 kHz

(CS5522/24/28) or 130 kHz (CS5521/23) can be used for increased throughput.

26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

28. Applicable when SCLK is continuously running.

Specifications are subject to change without notice.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

(Note 25)

External Clock or Internal Oscillator (CS5522/24/28)

(CS5521/23)

XIN

32.768

200

130

kHz

Master Clock Duty Cycle

Rise Times

(Note 26)

Any Digital Input Except SCLK

SCLK

Any Digital Output

trise

1.0

100

Fall Times

(Note 26)

Any Digital Input Except SCLK

SCLK

Any Digital Output

tfall

1.0

100

Start-up

Oscillator Start-up Time

XTAL = 32.768 kHz

(Note 27)

tost

-500

Serial Port Timing

Serial Clock Frequency

SCLK

MHz

SCLK Falling to CS Falling for continuous running SCLK

(Note 28)

100

Serial Clock

Pulse Width High

Pulse Width Low

250

SDI Write Timing

CS Enable to Valid Latch Clock

Data Set-up Time prior to SCLK rising

Data Hold Time After SCLK Rising

100

SCLK Falling Prior to CS Disable

100

SDO Read Timing

CS to Data Valid

150

SCLK Falling to New Data Bit

150

CS Rising to SDO Hi-Z

150

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